Real-world Blackbird does real-world stuff for Apache (really)

Let's call it a #ShowUsYourTalos moment. This video from Savoir Technologies shows off their own Blackbird system, carrying an 8-core POWER9 CPU with a 3U HSF, a 4-slot NVMe riser card, two 64GB DDR4 DIMMs and a 500W PSU running on the onboard ASPEED framebuffer.

But this machine isn't just a bragging rights toy: it provides substantial support for the Apache products Savoir works on. These are primarily Java-based and there are three main choices for JDKs on POWER9, in particular Adoptium's Temurin, Eclipse OpenJ9 (descended from IBM's original J9, which I personally run on my AIX POWER6), and Red Hat's build of OpenJDK. Savoir tests on all three.

As anyone working on Java will attest, it's not enough just to make sure it works on different JVMs. This machine is dedicated to improving ppc64le support, stability and performance actually on the architecture itself. (Linus would agree.) Savoir does multiple builds to tamp down broken unit tests and find glitches due to Power ISA's different memory model guarantees. One example they cite in the video was a stress test they did on this very box, running one billion SOAP requests through Apache CXF with no errors.

I'm not involved or linked to Savoir in any way; I'm just delighted to see real hardware in the real world doing real things for real people. Right now, I don't think you're going to get throughput like this from anything with the current crop of RISC-V chips in it, and I'm hopeful that S1 is still in the pipeline to give us the shot in the arm we need to stay ahead of the curve on open hardware.

Microwatt goes multiprocessor

It's been awhile since we dropped in on Microwatt, the OpenPOWER VHDL softcore. Microwatt now runs on multiple FPGA boards or can be run (slowly) in simulation, and is capable of booting Linux. Raptor uses Microwatt for the Arctic Tern soft BMC. Although it still doesn't support vector instructions, recent commits have added an FPU and many of the standard special-purpose registers, and the newest ones now add support for SMP.

The newest pull request, currently to be committed, allows more than one processor core to be created by adding an NCPUS option to soc.vhdl. These cores can be debugged separately with JTAG and have the same view of memory and the same timebase value, and can be individually activated. For interrupts, they each have their own presentation controller in the XICS.

Although Microwatt cores are currently of only modest performance, more cores — if you have the space — can certainly improve its throughput and the range of applications it could be practical for. Unfortunately, we've still yet to hear anything new about the Solid Silicon S1 or how libre Power11 will end up being. Hopefully as the Microwatt design gets more efficient, at least the very smallest Power ISA systems will now have some additional flexibilities to work with.