Debian 13 is out, which like most other architectures is one of the big three distros on ppc64le (which Debian calls ppc64el in accordance with its normal naming scheme). The current release is based on the LTS kernel 6.12, glibc 2.41 and systemd 257, and includes
GNOME 48,
KDE Plasma 6.3,
LXDE 13,
LXQt 2.1.0,
Xfce 4.20,
gcc 14.2,
LLVM-Clang 19,
bind 9.20,
Perl 5.40,
and Python 3.13. ppc64el is one of the supported seven architectures and boots directly on all current Raptor hardware. As with all kernels with a 4K page size, if you try to use KVM acceleration in QEMU with a 64K page size guest (the default), it will fail. This doesn't occur on Fedora because Fedora ships a kernel with a 64K page size. Fortunately, see this note for workarounds by either setting a 4K property on the guest or using a 64K page size on the OS side. Live and installer images are available.
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Power11 hits the market this month
It's notable that the "meet the family" document IBM links from the press release — so we can assume it's officially blessed — says nothing about OMI, only DDR5 RAM. However, IBM has made it clear that Power11 will continue to have OMI, since enterprise Power10 customers would certainly have had an investment in it, and the upper tier datasheets reference OMI channel capacity. We don't know if the OMI firmware for Power11 is open and libre (it was not in Power10), nor if the Synopsys IP blocks reportedly used in Power10's I/O are still present, because IBM didn't say, or if the "low-end" binned CPUs are different in this regard.
If there are going to be third-party Power11 systems, and IBM didn't say anything in the press release about them either, they generally follow six to twelve months after. We have heard little from Raptor since about the SolidSilicon S1 and X1, and because all indications suggest the S1 is a Power10 implementation without the crap, this already puts them behind the curve. That said, adapting Power11 should be possible to any next-generation Power ISA workstation: the Talos II and T2 Lite are fairly straightforward reworks of the reference POWER9 Romulus design, and Blackbird is still Romulus, just in a much smaller form factor. These first-generation P11 boxes, as presumably performant as they are, wouldn't be nice to have in an office and IBM just doesn't do end user sales. Creating a T3 based on Blueridge would seem to be the best way forward for Raptor to regain the top slot in OpenPOWER workstations — assuming the architecture is still open.
[UPDATE: I have been advised by an anonymous individual with knowledge of the situation that a new Raptor announcement on products under development is scheduled for Q1 2026 ... which would be "six to twelve months after" as predicted. "Open firmware" is specifically mentioned and absolutely planned. It's worth pointing out that both Raptor and SolidSilicon are now listed as top-tier Platinum members for OpenPOWER parallel with IBM itself. That implies SolidSilicon is still in the mix and IBM is still backing OpenPOWER. They stressed this is not an official announcement, so you take it for what it's worth.]
Enter the IBM z17 mainframe with Telum II (more clues for Power11?)
IBM is announcing their new z17 mainframe, based on the Telum II (see our notes on the original Telum CPU). IBM first announced the Telum II last year and the z17, its intended first deployment, has now emerged just about bang on time.
Still, we're obviously more interested in Power ISA around here, and IBM has yet to say much substantive about Power11 other than the usual assertions of additional power efficiency, more cores and higher clock. It is also expected to offer DDR5 support for enhanced memory bandwidth, though this is all but certain to require OMI DDR5, not direct-attached RAM as in our Raptor boxes. But it's often instructive to look at what's going on with IBM mainframes for microarchitectural clues now that Z-machines and IBM "big" Power chips often have the same underlying design.
Of course, the marketing material on z17 is all AI all the time. IBM's claimed AI improvements seem to descend from an enhanced "DPU" ("data processing unit") with its own 64K (32K instruction/32K data) L1 cache capable of 24 trillion INT8 operations per second, the kind of bolt-on hardware that could also be incorporated or scaled-down into other products. In fact, such a product exists already, shown above: IBM's Spyre Accelerator, which is basically 32 more DPUs. These attach over PCIe and would be a good alternative to our having to scrabble around with iffy GPU support, assuming that IBM supports this in Linux (but they already do for LinuxONE systems, so it shouldn't be much of a stretch).
The first Telum strongly emphasized cache. Interestingly, it did so by dropping categorial L3 and L4 altogether: instead, IBM developed a strategy where cores could reach into the L2 of other cores and treat that as L3, and reach into other chips' cache and treat that as L4. Each chip had eight cores and 32MB of L2 per core, giving lots of opportunity for more efficient utilization. The picture of the Telum II die above shows that IBM has not substantially deviated from this plan, using the same 128K/128K L1 but increasing L2 to 36MB per core. IBM's documentation says that there are eight cores per chip, but at a cursory glance there appear to be ten on the die, likely for yield reasons (two cores would be fused off). Assuming these dud cores still have useable cache, however, that matches IBM's specs of up to 360MB of effective L3 and a whopping 2.88GB of L4 per system.
The cores top out at 5.5GHz with various microarchitectural improvements such as better branch prediction and faster store writeback and address translation, all the typical kinds of tweaks that would also likely show up in Power11. Power11 is also expected to remain on 7nm with a "refined" process instead of moving to 5nm. (It's possible that Power12, whenever that arrives, may skip 5nm entirely.)
If you have the money and a convenient IBM salesdroid who actually answers the phone, you too can horrify your electrical utility starting in June. As for those of us on the small systems side, Power11 in whatever form it ends up taking is not anticipated to emerge until Q3 2025, presumably as what will be the E1100 series starting with the E1180 and going down. This further shrinks the production and sales window for the long-anticipated Raptor S1 systems, however, and there hasn't been a lot of news about those — to say nothing of what the Trump tariffs could mean for rolling out a new system.
Plan 9 finally comes to the POWER9
Also, I'm well aware of the calendar, thanks.
Real-world Blackbird does real-world stuff for Apache (really)
But this machine isn't just a bragging rights toy: it provides substantial support for the Apache products Savoir works on. These are primarily Java-based and there are three main choices for JDKs on POWER9, in particular Adoptium's Temurin, Eclipse OpenJ9 (descended from IBM's original J9, which I personally run on my AIX POWER6), and Red Hat's build of OpenJDK. Savoir tests on all three.
I'm not involved or linked to Savoir in any way; I'm just delighted to see real hardware in the real world doing real things for real people. Right now, I don't think you're going to get throughput like this from anything with the current crop of RISC-V chips in it, and I'm hopeful that S1 is still in the pipeline to give us the shot in the arm we need to stay ahead of the curve on open hardware.
Microwatt goes multiprocessor
The newest pull request, currently to be committed, allows more than one processor core to be created by adding an NCPUS option to soc.vhdl. These cores can be debugged separately with JTAG and have the same view of memory and the same timebase value, and can be individually activated. For interrupts, they each have their own presentation controller in the XICS.
Although Microwatt cores are currently of only modest performance, more cores — if you have the space — can certainly improve its throughput and the range of applications it could be practical for. Unfortunately, we've still yet to hear anything new about the Solid Silicon S1 or how libre Power11 will end up being. Hopefully as the Microwatt design gets more efficient, at least the very smallest Power ISA systems will now have some additional flexibilities to work with.