Musing over POWER9 roadmap at Hot Chips

(See the presentation from AnandTech's live blog at Hot Chips.)

With the news that GlobalFoundries has stopped all 7nm development, the next step for the Power ISA got more nebulous. IBM really phoned in their presentation at Hot Chips this time around; there wasn't a lot of meat on the bone, and they probably got advance warning of the changes at GF which likely cut what they were willing to say in public. But IBM still has one more stop on the roadmap for the POWER9, so they're not done with 14nm yet.

The 2019 "advanced I/O" POWER9 will increase memory bandwidth from the "scale up" 210GB/s to 350GB/s, over twice as much as the "scale out" cores in the Talos II at 150GB/s. IBM didn't appear to say if this would require buffering or if it was direct attached memory, though our incompletely informed suspicion here is the former. If so, it wouldn't be a direct replacement for the Sforza cores the T2 runs now; the board would probably need a redesign to accommodate whatever Centaur successor they require. That would also have power and thermal impacts in a workstation form factor. I/O on the "AIO" POWER9 jumps to OpenCAPI 4.0 from 3.0, allowing caching on accelerators and additional link widths, and NVLink 3.0 from 2.0, presumably both over Bluelink. IBM didn't announce clock speeds, but given that the core counts are the same, they're most likely identical or comparable.

IBM also said rather little about the POWER10. No core count was reported and the node size was pointedly not shown. However, signaling was announced at 32 and 50GT/s, up to double the POWER9, indicating IBM continues to prioritize bandwidth as their competitive advantage against x86 commodity servers. The timeframe is still 2020, so we can expect at least another 18 months of POWER9 goodness.